FTGMAC100_S provides AHB master capability. It fully complies with IEEE 802.3 specification for 10/100 Mbps Ethernet and IEEE 802.3z specification for 1000 Mbps Ethernet. FTGMAC100_S DMA controller handles all data transfers between system memory and on-chip memory. With the DMA engine, it could reduce the CPU loading, maximize the performance and minimize the FIFO size.
FTGMAC100_S has an on-chip memory for buffering; no external local-buffer memory is needed. It also supports both MII and GMII interfaces. The MII interface supports two specific data rates, 10 Mbps and 100 Mbps. The GMII interface supports data rate of 1000 Mbps.
In order to reduce the processing load of the host CPU, FTGMAC100_S implements TCP, UDP and IPv4 header checksum generation and validation, and supports VLAN tagging. For QoS and CoS requirements, FTGMAC100_S supports high priority queues to reduce the processing load of host CPU for transmitting packets.
The FTGMAC100_S provides Wake-on-LAN function. It supports three wake-up events: link status change, magic packet and wake-up frame. The function allows a system containing FTGMAC100_S to be waked up by remote side. The AHB wrapper allows users to quickly integrate FTGMAC100_S into their SoC design.
Features
- AHB bus interface supports bus master and slave mode
- DMA engine for transmitting and receiving packets
- Support TCP, UDP, IP header checksum offloads
- Support IEEE 802.1Q VLAN tag insertion and removal
- Support High Priority Transmit Queue for QoS and CoS applications
- Support Wake-on-LAN function with three wake-up events: Link status change, Magic packet and Wake-up frame
- Independent TX/RX FIFO
- Support half and full duplex (full duplex operation supported
only in 1000 Mbps mode)
- Support flow control for full duplex and backpressure for half duplex
- Spport MII/GMII interface
- Support Jumbo packets (9K bytes)
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